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The victory of the losers, or the story of the creation of FLASH memory (part4)
Our main goal was not to change anything during the production process, and to solve the problem of how to place electrons on a floating shutter. Initially, we abandoned the…

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Mobility Radeon от ATI
There is nothing surprising in the fact that the new Mobility Radeon is developed on the basis of the latest ATI graphics chip for desktop systems - Radeon VE, which,…

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The use of CAD “MAX + plus II” for the development of digital devices on FPGAs from Altera

CAD “MAX + plus II” is an integrated environment for the development of digital devices based on programmable logic integrated circuits (FPGAs) of Altera company and ensures the implementation of all stages necessary for the production of finished products:

creating device designs;
synthesis of structures and trace internal FPGAconnections;
preparing data for programming or configuring FPGAs (compilation);
project verification (functional modeling and time analysis);
programming or configuring FPGAs.
The procedure for obtaining and installing free versions of CAD “MAX + plus II”, as well as the main characteristics of Altera FPGAs supported by these versions, are given in the previous article.

The most complete corporate description of the MAX + plus II system is contained in the document MAX + plus II Getting Started Manual on the Altera website, which includes the tutorial (Tutorial). In Russian, a fairly detailed description of the MAX + plus II system can be found in [1]. This article provides the minimum amount of information necessary for the initial development of the technology for developing digital devices on FPGAs from Altera. As an example, the development process of a control device for a 7-segment LED indicator is considered.

MAX + plus II system applications
The package “MAX + plus II” includes the following interconnected applications that implement all of the above stages of development of digital devices on FPGAs from Altera:

Project input applications (project editors)
“Graphic Editor” is a graphic editor designed to enter a project in the form of a connection diagram of the symbol characters of elements extracted from standard library packages or from the user’s library.

Waveform Editor is a time diagram editor (some authors call this application a signal editor), which has a dual function: at the input stage it provides input of the project logic in the form of diagrams (diagrams) of input and output states, and at the modeling stage it provides input of test diagrams ( reference) input states of the simulated device and setting the list of tested outputs.

“Text Editor” – a text editor designed to create and edit text files containing a description of the project logic in the AHDL (Altera Hardware Description Language) device description language or in languages ​​similar to it like VHDL, “Verilog”. For mastering the AHDL language, one can recommend [1, 2], as well as articles published in a number of issues of Chipnews magazine in 2000.

“Symbol Editor” is a symbol editor that allows you to edit existing symbols and create new ones. By the way, any compiled project can be collapsed into a symbol, placed in a symbol library and used as an element in any other project.

“Floorplan Editor” is a communications editor (level-by-level scheduler), which allows you to manually distribute FPGA outputs (assign outputs to specific input and output signals) and redistribute some internal FPGA resources on the layout of the main logic elements.

MAX + plus II Compiler Applications
These are applications included in the compiler package and designed to synthesize the structure, trace connections, verify the correctness of the project and localize errors, generate programming files or configure FPGAs:

“Netlist Extractor” is an application that extracts the list of connections from the source file of the project view created when the project was entered.

“Database Builder” is an application designed to build a project database.

“Logic Synthesizer” is an application that provides verification of the correctness of the project according to formal rules and synthesis of the optimal structure of the project.

“Partitioner” – an application that provides the splitting of the project into parts in cases where the resources of one crystal (microcircuit) are not enough to implement the project.

“Fitter” is a tracer for internal connections that provides the implementation of a synthesized structure.

“SNF Extractor” is an application that provides the extraction of project parameters necessary for functional modeling and time analysis.

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