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The victory of the losers, or the story of the creation of FLASH memory (part2)
This type of memory was made in the form of a two-dimensional matrix of conductors, at the intersection of which a thin jumper (20-30 μm) was created from metal or…

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Athlon XP: not by number, but by reduction!

When this issue of the magazine was being prepared for publication, a remarkable event occurred: the next Microprocessor Forum. Probably, when you read this article, you already know that AMD in this forum revealed many details of the 64-bit architecture that will be implemented in Hammer processors, and talked about some of its other innovations. In addition, a new processor from AMD – Athlon XP – was officially presented at the forum.

Of course, Athlon XP is not such a revolutionary event as, say, the advent of 64-bit processors. However, Athlon XP processors should replace the now widespread Athlon line with the Thunderbird core used in productive workstations. Therefore, most of us will have to deal directly with this processor in the near future.

How is the Athlon XP processor different from all previous ones?

External differences
The new processor is noticeably different from its predecessor even in appearance.

Firstly, the processor crystal has now become not rectangular, but almost square.

Secondly, it is now installed on an organic material board (OPGA). The use of such materials is usually presented in brochures as another technological breakthrough. Nevertheless, in appearance this “organic material” painfully resembles the most ordinary fiberglass, which is widely used in the manufacture of printed circuit boards. It is no accident that the matching resistors and capacitors, which are located at Thunderbird on top and at a considerable distance from the processor chip, are now located at the bottom, in close proximity to it.
But in general, this, of course, is a certain technological achievement. At least, manufacturers have learned to use cheaper materials in the design of the processor.

Many, probably, are interested not so much in the appearance of the new processor, but in the question of where the very “bridges” are located with which you can “overclock” the processor. These bridges are also present in the new processor, which is clearly visible on. However, their location has changed compared to the previous model. But they are! And it pleases. True, their design has changed.

With a strong increase, it is clear that the jumpers themselves are now hidden under the top layer of plastic, although they are visible through a translucent coating. Most likely, the bridges are fired by a laser beam, while ugly scars remain, clearly visible in the photograph. But on the whole, these innovations are unlikely to stop our youth, and probably soon we will find out where to rub with a pencil and where with an elastic band so that XP “flies” even faster.

Internal differences
The Athlon XP processor differs from its predecessor not only externally. The new processor received a new core – Palomino. Of course, Thunderbird also had a great kernel. In terms of performance, Athlon has long been ahead, for example, of the Pentium 4 at the same core clock speed. But the Thunderbird core has a frequency limit of 1.4 … 1.5 GHz, while the Pentium 4 has successfully overcome the 2 GHz bar. Therefore, in order to win not by number, but by reduction, it was necessary to take extraordinary steps. First of all, the core of the new processor was redone. These were quite profound changes, and not just cosmetic improvements.

So, in particular, the mechanism for translating command and data addresses to physical memory addresses underwent a significant alteration. To speed up access to commands and data, all modern processors have Translation Look-aside Buffer (TLB). This buffer caches, but not the data or instructions, but their physical addresses. In previous Athlon processors, this buffer was two-level. The first level (L1) – with a capacity of 24 values ​​for instruction addresses and 32 values ​​for data addresses. The second level (L2) could store up to 256 data addresses and 256 instruction addresses.

The size of the first level buffer has been increased in the Palomino core, now it can store up to 40 data address values. In addition, now TLB, as well as the main cache, has become “exclusive” – ​​exclusive. This means that the contents of the first level buffer do not duplicate the contents of the second level buffer. And, finally, the new kernel implements a mechanism for accelerating the loading of new address values ​​(before they may be required) – speculatively reload.

Significantly improved the mechanism of forward loading of data from memory to the cache. The advanced data loading mechanism was also implemented in early processors, but only for instructions included in 3DNow! and SSE. For applications optimized for the 3DNow! Command system or SSE, this gave a significant gain in performance. But for non-optimized applications, faster data loading was not possible.

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